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Preliminary Data Sheet
Rev.0.9
20.09.2011
Parameter
& Test Condition
OPERATING WRITE CURRENT:
All device banks open, Continuous burst writes; One
Symbol
I DD4W
10600-999
945
max.
8500-777
810
Unit
mA
module rank active; BL = 4, CL = CL (I DD ), AL = 0;
t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD );
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
t CK = t CK (I DD ); refresh command at every t RFC (I DD )
I DD5
2610
2160
mA
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
I DD6
270
270
mA
Address bus inputs are floating at V REF ; DQ’s are
floating at V REF
OPERATING CURRENT*) :
Four device bank interleaving READs, I OUT = 0mA; BL = 4,
CL = CL (I DD ), AL = t RCD (I DD ) – 1 x t CK (I DD ); t CK = t CK
I DD7
1665
1305
mA
(I DD ), t RC = t RC (I DD ), t RRD = t RRD (I DD ), t RCD = t RCD (I DD );
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR I DD MEASUREMENT
I DD MEASUREMENT CONDITIONS
SYMBOL
CL (I DD )
t RCD (I DD )
t RC (I DD )
t RRD (I DD )
t CK (I DD )
t RAS MIN (I DD )
t RAS MAX (I DD )
t RP (I DD )
t RFC (I DD )
10600-999
9
13.5
49.5
6
1.5
36
70’ 200
13.5
351
8500-777
7
13.125
50.625
7.5
1.87
37.5
70’ 200
13.125
350.625
Unit
t CK
ns
ns
ns
ns
ns
ns
ns
ns
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 8
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